# Constraint files
export CONSTRAINT_FILES =  constraints_clock.tcl     \
                           constraints_global.tcl    \
                           constraints_pinning.tcl   \
                           constraints_placement.tcl


TOP_ENTITY := $(shell basename $(TOP_FILE))
TOP_ENTITY := $(patsubst %.v,%,$(TOP_ENTITY))
export TOP_ENTITY := $(patsubst %.vhd,%,$(TOP_ENTITY))


PROJECT_SOF  = $(TOP_ENTITY).sof
PROJECT_DONE = $(TOP_ENTITY).done

.PHONY: clean all

all: $(PROJECT_SOF)

# As quartus does "smart compilation" the ".sof" file
# modification date is not always changed, whereas the ".done"
# file is modified every time.
$(PROJECT_SOF): $(PROJECT_DONE)

# Synthesis flow

$(PROJECT_DONE): $(SOURCE_FILES) $(CONSTRAINT_FILES)
	@quartus_sh -t syn.tcl

# Programming Through the JTAG port of the FPGA
program:$(PROJECT_SOF)
	quartus_pgm -c DE-SoC -m jtag  -o "p;$<@2" -o "s;SOCVHPS@1"


# Cleaning

EXTS = asm.rpt     \
       done        \
       fit.rpt     \
       map.rpt     \
       fit.smsg    \
       map.smsg    \
       fit.summary \
       flow.rpt    \
       map.rpt     \
       map.summary \
       pow.rpt \
       pow.summary \
       jdi         \
       qws         \
       sdc         \
       pin         \
       pof         \
       qpf         \
       qsf         \
       sof         \
       qdf        \
       tis_db_list.ddb \
       sld      \
       sta.rpt     \
       sta.summary \
       merge.rpt   \
       tan.rpt     \
       tan.summary

define _clean_
clean::
	@rm -f $(TOP_ENTITY).$(1)
endef

$(foreach ext,$(EXTS),$(eval $(call _clean_,$(ext))))

clean::
	@echo "----> Cleanning synthesis directory of $(TOP_ENTITY)'s project"
	@rm -rf db
	@rm -rf incremental_db
